Method of making low leakage N-channel SOS transistors utilizing positive photoresist masking techniques

ABSTRACT

A self-aligned method of implanting the edges of NMOS/SOS transistors is described. The method entails covering the silicon islands with a thick oxide layer, applying a protective photoresist layer over the thick oxide layer, and exposing the photoresist layer from the underside of the sapphire substrate thereby using the island as an exposure mask. Only the photoresist on the islands&#39; edges will be exposed. The exposed photoresist is then removed and the thick oxide is removed from the islands edges which are then implanted.

The invention described herein was made in the performance of work underNASA Contract No. NAS8-31986 and is subject to the provisions of Section305 of the National Aeronautics and Space Act of 1958, (72 Stat. 435; 42U.S.C. 2457).

BACKGROUND OF THE INVENTION

The present invention relates to integrated circuits, particularly tointegrated circuits manufactured using silicon-on-sapphire (SOS)technology.

A problem has heretofore existed in controlling the leakage of theN-channel (NMOS) transistor in complementary symmetry metal oxidesemiconductor (CMOS) SOS integrated circuits or in NMOS/SOS integratedcircuits when the threshold voltage of the NMOS transistor is very low.The reason for the problem's existence is that every open geometry, i.e.non C² L, transistor manufactured using SOS technology really consistsof three transistors in parallel. The three transistors are a toptransistor manufactured on the flat upper surface of the silicon island,i.e. on a silicon surface which is parallel to the (100)crystallographic plane and a pair of "edge transistors" which aremanufactured on the edge of the island, i.e. on a silicon surfaceparallel to the (111) crystallographic plane. Since the edge transistorson the (111) silicon have a threshold voltage approximately 0.7 volts to1.0 volt lower than the top transistor, there is normally no problemwhen the integrated circuit is operated from a standard power supplyvoltage in the range of from 5 to 10 volts. The reason that there isnormally no problem is that the top N-channel transistor threshold isgenerally set to be at least 1.5 volts, so the edge transistors areturned off when the top transistor is turned off. However, there will bea problem if the threshold voltage of the top transistor is reduced tobelow about 1.0 volt for low voltage operation. There will also be aproblem if the N-channel transistors' thresholds shift due to radiationexposure. Then, the associated shift in the threshold voltage of (111)edge transistors is even greater than that of the top transistor, andthe shift can cause the edge transistors to go well into the depletionrange. The shift in threshold voltage of the edge transistors is a majorcause of post-radiation leakage current in SOS arrays.

In order to avoid the problems set forth above, the edge transistorleakage could be controlled by providing a guardband, i.e. a heavilydoped region, around the edge of the island in order to raise thethreshold voltage of the edge transistors by increasing their surfaceimpurity concentrations. This has generally not been done in the past,because no way of doing it which would not consume extra area andinvolve an additional photomask step was known heretofore.

Heretofore various approaches have been utilized in manufacturing lowleakage NMOS/SOS transistors. Such approaches are described more fullyin U.S. Pat. No. 3,890,632 entitled STABILIZED SEMICONDUCTOR DEVICES ANDMETHOD OF MAKING SAME, which issued to W. E. Ham et al. on June 17,1975; U.S. Pat. No. 4,178,191 entitled PROCESS OF MAKING A PLANAR MOSSILICON-ON-INSULATING SUBSTRATE DEVICE, which issued to D. W. Flatley onDec. 11, 1979; U.S. Pat. No. 4,070,211 entitled TECHNIQUE FOR THRESHOLDCONTROL OVER EDGES OF DEVICES ON SILICON-ON-SAPPHIRE, which issued to E.Harari on Jan. 24, 1978; and co-pending U.S. patent application No.093,011 entitled LOW LEAKAGE N-CHANNEL SOS TRANSISTORS AND METHOD OFMAKING THEM OF J. J. Fabula which issued on Feb. 24, 1981 as U.S. Pat.No. 4,252,574. Each of the aforementioned patents and patent applicationis incorporated herein by reference.

SUMMARY OF THE INVENTION

The threshold voltage of the parasitic NMOS edge transistors isincreased by increasing the well implant dosage at the edges of the NMOSepitaxial islands. To be effective, the increased ion implantation mustgo only into the edges of the NMOS transistors. Accordingly, a precisealignment is required. In accordance with the invention, a self-alignedtechnique for defining an ion implantation mask comprises the depositionof a thick oxide over the epitaxial islands. The oxide film must bethick enough to shield the upper surface of the island from the implant.The oxide film is coated with positive photoresist which is exposed fromthe back of the sapphire wafer, thereby using the epitaxial siliconisland as a self-aligned mask in the definition of the photoresistlayer.

The exposed photoresist is developed and used as a mask in the etchingof the silicon dioxide film. Careful over-etching of the oxide layerresults in the edge of the epitaxial island extending beyond the edge ofthe oxide layer. The edge implantation is then performed.

BRIEF DESCRIPTION OF THE DRAWING In the drawing

FIG. 1 is a perspective view of the transistor manufactured inaccordance with the present invention;

FIG. 2 is an electrical schematic representation of the transistor ofFIG. 1; and

FIGS. 3-5 are cross-sectional views illustrating the method of thepresent invention.

DETAILED DESCRIPTION OF AN EXEMPLARY EMBODIMENT

Referring now to FIG. 1, a silicon-on-sapphire (SOS) N-channel MOStransistor 10 is shown. The configuration of the transistor 10 isstandard in that the transistor 10 comprises an island 12 of epitaxialsilicon material formed on the surface 22 of a sapphire substrate 14 inthe conventional manner. The transistor 10 comprises a source 13, adrain 15, and a gate 20 which overlies a channel region. Both the source13 and the drain 15 are of heavily doped N-type material, and thechannel region (not shown), which underlies the gate 20, is of lightlydoped P type material. The entire surface of the epitaxial siliconisland 12 is covered with a thin silicon dioxide layer through whichcontact openings (not shown) can be made to provide contact to thesource 13 and to the drain 15. The oxide layer also acts as the gatedielectric of the transistor 10, as is well-known in the art.

In view of the manner in which the silicon island 12 is formed, namelyby etching, the edges 18 of the island 12 have planes which are parallelto the (111) crystallographic plane, whereas the top surface 16 of theisland 12 is parallel to the (100) crystallographic plane. As is knownin the art, transistors formed on the (111) silicon plane have lowerthreshold voltages than transistors formed on the (100) silicon plane,assuming that all other things are equal. In order to increase thethreshold voltage of the edge transistors, the edges 18 of the siliconisland 12, manufactured in accordance with the present invention, aremade to have a higher surface concentration of acceptor impurities thanthe surface 16 of the silicon island 12.

With reference to FIG. 2, the transistor 10 can be modeled as a toptransistor 28 in parallel with a pair of edge transistors 24, 26. Theedge transistors 24, 26 are formed on the (111) edges 18 of the island12, whereas the top transistor 28 is formed on the (100) top surface 16of the island 12. The increased surface concentration of acceptorimpurities in the edges 18 relative to the top surface 16 serves toincrease the threshold voltage of the edge transistors 24, 26 relativeto the top transistor 28.

Referring now to FIGS. 3-5, the method of the present invention will beexplained. The structure shown in FIG. 3 comprises a partially completedsilicon-on-sapphire transistor 10 in the middle of a standard processingsequence, of the type well-known in the art. The structure 10 comprisesa sapphire substrate 14 having a silicon layer 12 epitaxially grownthereon. The epitaxial layer is defined into silicon islands by using astandard photolithography step. Typically, a masking oxide layer isthermally grown on the surface of the silicon layer. Then, a photoresistlayer is deposited, defined, and developed. The developed photoresistlayer is then used as an etch mask for defining the silicon dioxidelayer. Then the defined silicon dioxide layer is used as a masking layerin an etch of the underlying silicon epitaxial layer, thereby leavingislands where transistors will be formed.

A silicon dioxide layer 32, preferably of deposited silicon dioxide, andhaving a thickness of between about 6000 angstroms and 10,000 angstromsis formed over the surface of the silicon island 12 and the surface ofthe sapphire substrate 14 in any standard manner. A layer 34 of apositive photoresist material overlies the silicon dioxide layer 32.

The structure 10 is subjected to an exposure of ultraviolet light fromthe underside of the substrate, i.e. through the wafer, (represented bythe arrows in FIG. 3). The back exposure exposes the photoresist layer34 through the sapphire substrate 14 and through the silicon dioxidelayer 32. However, the back exposure is selected to have an intensityand duration such that it will not expose the portions of thephotoresist layer 34 which overlie the silicon island 12. Thus, thephotoresist layer 34 will be exposed above areas of the sapphiresubstrate 14 having no epitaxial silicon islands 12 thereon, and thephotoresist layer 34 will be partially exposed over the edges 18 of theepitaxial island 12.

Following the exposure of the photoresist layer 34, the photoresistlayer 34 is developed and used as an etch mask in etching the silicondioxide layer 32. Following the etch, which is typically conducted inbuffered hydroflouric acid (HF), during which there will be undercuttingof the developed photoresist etch mask 34, the structure will appear asshown in FIG. 4.

Next, the photoresist layer 34 is removed, and the silicon dioxide layer32 is used as an implantation mask during the ion implantation ofimpurities such as boron, into the edges 18 of the silicon island 12 asshown in FIG. 5. We have found that a dose of 1.5×10¹² ions/cm² at anenergy level of 50 KeV is effective to reduce the edge leakage of theNMOS transistors.

At this point, normal SOS processing is resumed. Typically, the oxidelayer 32 will be stripped. Then, a new oxide layer (the gate oxide) willbe grown over the surface of the island 12. The gate 20, typically ofdoped polycrystalline silicon will be applied, defined, and doped tomake it conductive. Then, contact openings will be formed to allowcontact to the source 13 and drain 15. A metallization layer will thenbe applied and defined, and a protective oxide will be formed thereover.Finally, bond pad openings will be formed in the protective oxide layerin the standard manner.

We claim:
 1. An improved method for forming an SOS FET device havingsource and drain regions of a given conductivity type, comprising thesteps of: (i) epitaxially growing a silicon layer on the top side of asapphire substrate;(ii) forming a masking layer on the surface of thesilicon layer, the masking layer covering the area of the silicon layerwhere at least one island which will be used for forming a transistor islocated; and (iii) removing the portions of the epitaxial silicon layerwhich are not under the masking layer in order to leave the islands onthe top side of the sapphire substrate; wherein the improvementcomprises: (a) forming a transparent masking layer over the surface ofthe silicon island and the exposed portions of the sapphire substratebetween the islands; (b) applying a positive photoresist layer over thetop surface of the transparent masking layer; (c) exposing thephotoresist layer from the underside of the substrate, whereby onlythose portions of the photoresist layer which overlie the edges of theislands and those portions of the photoresist layer which lie betweenthe islands will be exposed, but only those portions of the photoresistlayer which overlie the top surface of the islands will not be exposedthrough the islands; (d) developing the photoresist layer; (e) removingonly those portions of the transparent masking layer which are on thesides of and between the islands that are exposed when the photoresistlayer is developed; (f) removing the photoresist layer remaining on theunremoved portions of the transparent masking layer; and (g) implantingconductivity modifying ions of a type opposite to that of the source anddrain regions into the exposed edges of the islands.
 2. The method ofclaim 1, wherein:The SOS FET device is an N-Channel transistor; and theimplanted conductivity modifying ions are boron.
 3. The method of claim1 wherein said step of forming a transparent masking layer over thesurface of said islands comprises forming a silicon dioxide layer overthe surface of said islands.
 4. The method of claim 3 wherein said stepof forming a silicon dioxide layer over the surface of said islands isaccomplished by the thermal oxidation of the silicon islands.
 5. Themethod of claim 3 wherein said step of forming a silicon dioxide layerover the surface of said islands is accomplished by depositing a silicondioxide layer over the surface of said islands and said substrate. 6.The method of claim 1 wherein the step of removing the portions of saidtransparent masking layer which are exposed when said photoresist layeris developed is accomplished by etching.
 7. The method of claim 6wherein said transparent masking layer is comprised of silicon dioxide,and said step of removing portions thereof is accomplished by etching ina solution of buffered hydroflouric acid (HF).
 8. The method of claim 7wherein said step of removing portions of the transparent masking layerincludes etching for a time sufficient to undercut said developedphotoresist layer.